An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Sparse Matrix-Vector Multiplication (SMVM) is a fundamental core of many high-performance computing applications, including information retrieval, medical imaging, and economic modeling. While the use of reconfigurable computing technology in a high-performance computing environment has shown recent promise in accelerating a wide variety of scientific applications, existing SMVM architectures on FPGA hardware have been limited in that they require either numerous pipeline stalls during computation (due to zero padding) or excessive input preprocessing during the run-time.
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