Provided by: Scientific Research Publishing
Date Added: Jul 2014
In this paper, the authors describe microprogrammed architecture for an embedded co-processor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures and explains how to expand the supported test command set. The co-processor uses a Fast Simplex Link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan- 6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: the full IEEE 1149.1 structural test operations and a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.