International Journal of Computer Science and Information Technologies
As more and more IP cores are integrated into a System-on-Chip (SoC) design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The on-chip bus design can be divided into two parts, namely the interface and the internal architecture of the bus. In this paper a well-defined interface standard, the Open Core Protocol (OCP), has adopted to design the internal bus architecture. Efficient bus architecture to support most advanced bus functionalities defined in OCP has been developed.