An Improved Masked S-Box for AES and Hardware Implementation

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Provided by: AICIT
Topic: Hardware
Format: PDF
Masking in gate level is popularly used to protect AES S-box against power analysis attacks. But there still exists a kind of attack, called glitch attack, to achieve the sensitive information from gate cell leakage. Some works had been done to resist against glitch attack, which carefully masked AND gate or used Wave Dynamic Differential Logic (WDDL) cell. In this paper, the authors propose an improved masked AND gate, in which the relationship between inputs masked values and masks, is nonlinear.
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