An Improved Optimization Techniques for Parallel Prefix Adder Using FPGA
In this paper, carry tree adders are proposed. Parallel prefix adders have the best performance in VLSI Design. Parallel prefix adders give the best performance compared to the Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). Here delay measurements are done for Kogge-Stone (KS) adder, Sparse Kogge-Stone (SKS) adder and spanning tree adder. Speed of KS adder and SKS adder have improved compared to the Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). Model simulator-Altera 6.6d and Xilinx 10.1 tools were used for simulation and synthesis of the design.