An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support

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Provided by: edaa
Topic: Hardware
Format: PDF
Sophisticated C compiler support for Network Processing Units (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level code compilation always introduces overhead, regarding code size and performance compared to handwritten assembly code. These overhead results partially from high-level function calls that usually introduce memory accesses in order to save and reload register contents. A key feature of many NPU architectures is hardware multithreading support, in the form of separate register files, for fast context switching between different application tasks.
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