An NoC Traffic Compiler for Efficient FPGA Implementation of Parallel Graph Applications

Provided by: California Institute of Technology
Topic: Hardware
Format: PDF
Parallel graph algorithms expressed in a Bulk-Synchronous Parallel (BSP) compute model generate highly-structured communication workloads from messages propagating along graph edges. The authors can expose this structure to traffic compilers and optimization tools before runtime to reshape and reduce traffic for higher performance (or lower area, lower energy, lower cost). Such offline traffic optimization eliminates the need for complex, runtime NoC hardware and enables lightweight, scalable FPGA NoCs. In this paper, they perform load balancing, placement, fan-out routing and fine-grained synchronization to optimize their workloads for large networks up to 2025 parallel elements.

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