An Novel Methodology for Reducing SoC Test Data Volume on FPGA-Based Testers

Provided by: edaa
Topic: Hardware
Format: PDF
Low-cost test methodologies for systems-on-chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in order to guarantee high test quality, while minimizing application costs. Consequently, low-cost test strategies can be run on testers offering lower performance and/or reduced features with respect to traditional Automatic Test Equipments (ATEs); these equipments are usually referred to as low-cost testers. This paper proposes a methodology for reducing the test data volume for the application of SoC low-cost test procedures.

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