An on Chip Hindrance Computation Skill for Small Delay Deficiency Revealing Using Signature Registers

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Provided by: International Journals of Advanced Information Science and Technology (IJAIST)
Topic: Data Management
Format: PDF
Efficient test and debug Techniques are indispensable for performance characterization of large complex integrated circuits. In this paper the authors present an on line scheme for latency fault revealing, where delay is quantized by a technique using signature registers which measures the delay of explicitly sensitized paths with the resolution of the on-chip variable clock generator. Small Delay Defects are recognized by means of a scan design which apprehend complete on-chip delay measurement in short time.
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