An On-Chip Metastability Measurement Circuit to Characterize Synchronization Behavior in 65nm

Provided by: Institute of Electrical & Electronic Engineers Topic: Data Centers Date Added: Jun 2011 Format: PDF
Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm circuits and beyond. An on-chip metastability measurement circuit was fabricated in a 65nm 1.1V bulk CMOS. A fully digital on-chip measurement system is presented here that helps to characterize synchronizers in future technologies. Different types of synchronizers were measured and compared. The standard library FF is demonstrated to have lower tau value than various feedback flip-flops.

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