Institute of Electrical & Electronic Engineers
An optimal linear time algorithm for interprocedural register allocation in high-level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is NP-complete in general; however, converting each procedure to Static Single Assignment (SSA) Form ensures a chordal interference graph, which can be colored in O(|V|+|E|) time; the interprocedural interference graph (IIG) is not guaranteed to be chordal after this transformation. An extension to SSA Form is introduced which ensures that the IIG is chordal, and the conversion process does not increase its chromatic number. The resulting IIG can then be colored in linear time.