An RDL-Configurable 3D Memory Tier to Replace On-Chip SRAM

Provided by: edaa
Topic: Storage
Format: PDF
In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system designs. Previously proposed dynamic re-configurable solutions demonstrate strong dependence between read latency and dimensions of the mapped memory, leading to potential performance limitations. In this paper, the authors propose a one-time configurable memory tier designed to minimize the performances overhead due to the commodity.

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