An Ultra Low-Power TLB Design

Provided by: edaa
Topic: Storage
Format: PDF
This paper presents an ultra low-power TLB design, which combines two techniques to minimize the power dissipated in TLB accesses. In the authors' design, they first propose a real-time filter scheme to eliminate the redundant TLB accesses. Without delay penalty the proposed real-time filter can distinguish the redundant TLB access as soon as the virtual address is generated. The second technique is a banking-like structure, which aims to reduce the TLB power consumption in case of necessary accesses. They present two adaptive variants of the banked TLB. Compared to the conventional banked TLB, these two variants achieve better power efficiency without increasing the TLB miss ratio.

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