Analog Phase Lock Loop using CMOS Ring Oscillator in 22 nm Technology

Provided by: International Journal of Innovative Science Engineering and Technology (IJISET)
Topic: Hardware
Format: PDF
The phase locked loop is a versatile device which founds its application in many analog and digital electronic devices. In this research paper, the authors aim at designing a schematic layout of Type I PLL in 22 nanometer process parameter using Microwind 3.1. The VCO used is generating 2.8GHz frequency and is providing the feedback to phase detector circuit. The PLL designed is generating 1.8-2.8GHz frequency with reference signal of 2.4GHz and a clock of more than 120MHz.

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