In this paper, the authors design a high speed low power VLSI adder subsystem, for usage in ASIC's and low power and high speed applications. The speed performances in several ASICS rely on adder's performance. In this design, an error tolerant adder subsystem is proposed. The proposed paper also involves the study of various adders, power delay comparison and study for design of full adders with optimum number of transistors to increase speed of the circuits. The design is approached through backend EDA tools (cadence/synopsis) under real time simulation conditions.