Adders are very important component of arithmetic and logical unit use in processors and digital computer systems. They are extensively use in basic digital operations such as subtraction, multiplication and division. The performance of adder operation is analyzed by its power dissipation, layout area and its operating speed. The major drawback of the parallel adder is its slow speed due to the time it takes to propagate the carry. To overcome this limitation, the authors propose the Carry Look-ahead Adder (CLA) design by using transmission gates which solves this problem by calculating the carry signals in advance, based on the input signals.