Provided by: International Journal of Engineering Sciences & Research Technology (IJESRT)
Date Added: Sep 2013
The analysis and design of a 100% and 87.5% high-performance and efficient memory element (flip-flop) capable of being selected for the purpose of reading from and writing into it, is of crucial importance in modern digital applications such as the Very large Scale Integrated (VLSI) circuits. The optimization of existing structures is necessary when the requirement of the flip-flops is for low-power, high-speed or low-noise applications. In this paper, the optimization of the existing flip-flops (SR and JK) is investigated to ascertain their utilization rate.