Analysis and optimization of Boundary-scan Test Circuit Designed for FPGA

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
Boundary scan is a widely adopted DFT (Design For Test). According to the characteristic of FPGA application, boundary-scan has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and IC level access capabilities of boundary-scan, its use has expanded beyond traditional board test applications into product design and service in this paper a test procedure for analysis of linear-feedback shift register and feedback shift register for FPGA application is proposed.
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