Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors

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Provided by: Linkoping University
Topic: Hardware
Format: PDF
In this paper, the authors propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. They trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. They propose a System Failure Probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software.
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