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The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transistors per chip mark. However various new reliability challenges such as Process Variation (PV) have emerged that can no longer be ignored by chip designers. In this paper, the authors provide a comprehensive analysis of the effects of PV on the microprocessor's Issue Queue. Variations can slow down issue queue entries and result in as much as 20.5% performance degradation. To counter this, they look at different solutions that include instruction steering, operand- and port-switching mechanisms.