Analysis of Area - Delay Low Power Adders in QCA Using VHDL Code

Provided by: The International Journal of Innovative Research in Computer and Communication Engineering
Topic: Hardware
Format: PDF
As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. The physical limit can be overcome by using the approach Quantum-dot Cellular Automata (QCA). In this brief, the authors propose a new adder that outperforms all state-of-the-art competitors and achieves the best area-delay tradeoff. The 64-bit version of the novel adder spans over 18.72 µm2 of active area and shows a delay of only nine clock cycles, that is just 36 clock phases.

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