Provided by: International Journal on Electronics & Communication Technology (IJECT)
Date Added: Dec 2011
In this paper, the authors simulated different adder cells using mentor graphics in 0.18Î¼m, CMOS technology. Analysis is done on as how the variation in parameters of CMOS effects the most important parameters of a circuit i.e. delay in producing the result and the power consumed by the circuit in generating that result. This paper demonstrates the delay and power consumption of the proposed adders, and the comparison results among different full adders. It has been observed that by changing the width of the CMOS the delay parameter is improved if they move towards the ideal condition whereas the increase in width increases the size of the CMOS used.