Analysis of High Performance FIR Filter Using Improved Distributed Arithmetic

Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, when the DA (Distributed Arithmetic) algorithm is directly applied on FPGA (Field Programmable Gate Array) to realize FIR (Finite Impulse Response) filter, it is difficult to achieve the best configuration in the co-efficient of FIR filter, the storage resource and the computing speed. When computational resources are limited, especially multipliers, Distributed Arithmetic (DA) are used in lieu of the typical multiplier-based filtering structures. The bottleneck is updating the memory table. Several attempts have been done to accelerate updating the memory, but at the expense of additional memory usage and of convergence speed.

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