University of California
Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in aggressive CMOS processes. This paper considers challenges and opportunities in identifying this variation and methods to combat it for improved computing systems. The authors introduce the notion of Instruction-Level Vulnerability (ILV) to expose variation and its effects to the software stack for use in architectural/compiler optimizations. To compute ILV, they quantify the effect of voltage and temperature variations on the performance and power of a 32-bit, RISC (Reduced Instruction Set Computing), in-order processor in 65nm TSMC technology at the level of individual instructions.