Analysis of New Dynamic Comparator for ADC Circuit
Comparator is the main basic device mostly used in Analog to Digital Converters (ADC). For the better transmission of signals, requirement of fastest analog to digital converters are required. So the new dynamic comparator is replaced in the place of existing comparator of analog to digital converter for the better conversion. This is designed and the performance is evaluated using CADENCE GPDK 180nm technology in LINUX environment. The clock frequency of new ADC circuit is increased from 200MHZ to 250MHZ and voltage is reduced from 1.2v to 0.2v.