Analysis of Power and Stability of 7T SRAM Cell
In this paper, the authors address a novel Seven Transistor (7T) CMOS SRAM cell design to enhance the stability, reduce dynamic power, leakage power and area in various applications. The designed cell has an inbuilt mechanism for charge sharing, by which power has been saved for write operation. The proposed 7T SRAM cell uses charging/ discharging single Bit Line (BL) mechanism, which results in reduction in the dynamic power consumption. In this work the stability has been studied and calculated by N-curve method. The measured results have reduced 10.88% and 47.18% of leakage and dynamic power respectively. Moreover the area is reduced by 12.15%.