Design procedure for multi-stage CMOS op-amp with features of fast settling and low power consumption is present in this paper. This paper is focused on optimum compensation by means of proper placement of poles and zero. Single-stage cascode amplifier is no longer suitable in low-voltage designs. So, that multi-stage amplifier is required with advance in technologies. To reduce the settling time and find the high gain in multi-stage op-amp, main aim is minimum MOS used in this technology.