Provided by: Creative Commons
Date Added: Apr 2015
In this paper, a novel high speed analysis of SRAM circuit that employs adiabatic charging of a word line during a read operation was found to provide a large Dynamic Noise Margin (DNM) for reading and CAM memory by using a reordered overlapped search mechanism for high-throughput low-energy. In the authors' circuit implementation in CAM memory cell, each word circuit is independently controlled by a locally generated timing signal rather than a global signal. In SRAM an analysis of the time-wise change in DNM revealed that the read noise margin of this circuit was 1.9 times larger than that of a conventional two-BL circuit.