Analysis of the Effect of Temperature and Power Dissipation Variations in SRAM Cells

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
With the increment of mobile, biomedical and space applications, digital systems with low-power consumption are required. As a main part in digital systems, low-power memories are especially desired. Reducing the power supply voltages to sub-threshold region is one of the effective approaches for ultra-low-power applications. The on-chip caches can reduce the speed gap between the processor and main memory. These on-chip caches are usually implemented using SRAM cells. In SRAM cell stand by leakage power has become a major issue in modern low power fabrication with technology scaling and for high temperature operations.
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