Analytical Approach for Enhanced Residue Modular Multiplier for Cryptography

Provided by: International Journal Of Engineering And Computer Science
Topic: Security
Format: PDF
In this paper, the authors present an implementation of VLSI architecture for Dual Field Residue Arithmetic modular multiplier with less delay based on finite field arithmetic to support all public key cryptographic applications. A new method for incorporating Residue Number System (RNS) and Polynomial Residue Number System (PRNS) in modular multiplication is derived and then implemented VLSI architecture for dual field residue arithmetic modular multiplier with less delay. This architecture supports the conversions, modular multiplication for polynomials and integers and modular exponentiation in same hardware.

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