Analytical Router Modeling for Networks-on-Chip Performance Analysis

Provided by: edaa
Topic: Hardware
Format: PDF
Networks-on-Chips (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, the authors present a generalized router model and then utilize this novel model for doing NoC performance analysis.

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