Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device

Provided by: The International Journals of Engineering & Sciences (IJENS)
Topic: Hardware
Format: PDF
The optimization of 45nm NMOS device was studied using Taguchi Method. This method was used to analyze the experimental data in order to get the optimum results. In this paper, there are four factors were varied for 3 levels to perform 9 experiments. Silicide on the poly-Si gate electrode was used to reduce the gate electrode resistance. The virtually fabrication of 45nm NMOS device was performed by using ATHENA module. While the electrical characterization of device was implemented by using ATLAS module.

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