International Journal of Computer Applications
An efficient simulation of Application Specific Instruction-set Processors (ASIP) is a challenging onus in the area of VLSI design. This paper reconnoiters the possibility of use of ASIP simulators for ASIP Simulation. This proposed paper allow as the simulation of the cache memory design with various ASIP simulators like Simple scalar and VEX. In this paper the authors have implemented the memory configuration according to desire application. These simulators performs the cache related results such as cache name, sets, cache associativity, cache block size and cache replacement policy according to specific application.