Applying the Zeros Switch-Off Technique to Reduce Static Energy in Data Caches

Provided by: Universidad Politecnica de Madrid
Topic: Hardware
Format: PDF
Cache memories occupy a high percentage of silicon area. This fact has motivated a large number of research works to be focused on alternative organizations of conventional caches: if the cache area is reduced without losing performance, the corresponding space can be dedicated to improve other processor parts. Recently, the situation has changed due to technology advances, and the critical problem is not the available area. On-chip level 3 caches have reached 6MB in some cases, and their area sometimes exceeds processor core size.

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