Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
In this paper, the authors present a case study of their chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. They first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how they approach these limits through a combination of microarchitecture and circuit techniques. Their 1.1V 1GHz NoC chip achieves 1-cycle router-and-link latency at each hop and energy-efficient router-level multicast support, delivering 892Gb/s (87.1% of the theoretical bandwidth limit) at 531.4mW for a mixed traffic of unicasts and broadcasts.

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