European Design and Automation Association
Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck of density improvement. In this paper, the authors propose a novel common-source-line array architecture, which uses a shared source-line along the row, leaving only one bitline per column. They also elaborate their design flow towards a reliable common-source-line array design, and demonstrate its effectiveness on STT-MRAM and memristor memory arrays.