Architecting Reliable Multi-Core Network-on-Chip for Small Scale Processing Technology

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Provided by: University of Florence
Topic: Hardware
Format: PDF
The trend towards multi/many-core design has made Network-on-Chip (NoC) a crucial component of future microprocessors. With CMOS processing technologies continuously scaling down to the nanometer regime, effects such as Process Variation (PV) and Negative Bias Temperature Instability (NBTI) significantly decrease hardware reliability and lifetime. Therefore, it is imperative for multi-core architects to consider and mitigate these effects in NoCs implemented using small-scale processing technology. This paper reports on a first step to optimize NoC architecture reliability in light of both PV and NBTI effects.
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