Architectural Exploration of 3D FPGas Towards a Better Balance Between Area and Delay

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Provided by: edaa
Topic: Hardware
Format: PDF
The emerging 3D technology, which stacks multiple dies within a single chip and utilizes Through-Silicon Vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Similarly, a generic 2D FPGA architecture can evolve into a 3D one by extending its signal switching scheme from 2D to 3D by means of TSVs. However, replacing all 2D Switch Boxes (SBs) by 3D ones with full vertical connectivity is found both area-consuming and resource-squandering.
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