Architectural Support for Handling Jitter in Shared Memory based Parallel Applications

Provided by: Indian Institute of Technology Delhi
Topic: Hardware
Format: PDF
With an increasing number of cores per chip, it is becoming harder to guarantee optimal performance for parallel shared memory applications due to interference caused by kernel threads, interrupts, bus contention, and temperature management schemes (referred to as jitter). The authors demonstrate that the performance of parallel programs gets reduced (up to 35.22%) in large CMP based systems. In this paper, they characterize the jitter for large multi-core processors, and evaluate the loss in the performance.

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