Provided by: International Journal of Engineering and Advanced Technology (IJEAT)
Date Added: Apr 2015
Network-on-Chip (NoC) architecture provides a good way of realizing efficient Interconnections in multiprocessors. 3D NoC uses a mesh topology with wormhole switching and stall-go flow control scheme. It improves scalability, diminished concurrent communication and low power consumption. NoC communication is realized by data packets and forwarded among the network which routes according to Look-Ahead-XYZ (LA-XYZ) routing algorithm. The proposed paper focuses on design and verification of 4x4x4 3D NoC. The proposed 3D NoC is designed in VHDL language at RTL level and verified on Xilinx using ISE 14.1 tools.