Architecture Supported Synchronization-Based Cache Coherence Protocol For Many-Core Processors

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Provided by: The University of Tulsa
Topic: Hardware
Format: PDF
The efficient support of cache coherence is extremely important to design and implement many-core processors. In this paper, the authors propose a synchronization-based coherence protocol to efficiently support cache coherence for shared memory many-core architectures. The unique feature of their scheme is that it doesn't use directory at all. Inspired by scope consistency memory model, their protocol maintains coherence at synchronization point. Within critical section, process cores record write sets with bloom-filter functions. When the core releases the lock, the write set is transferred to a synchronization manager.
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