Area and Speed Wise Superior Vedic Multiplier for FPGA Based Arithmetic Circuits

Provided by: International Journal of Computational Engineering Research (IJCER)
Topic: Hardware
Format: PDF
The speed of a multiplier is very important to any Digital Signal Processor (DSPs). Vedic Mathematics is the earliest method of Indian mathematics which has a unique technique of calculations based on 16 formulae. This paper presents the efficiency of Urdhva Triyagbhyam Vedic method for multiplication, which strikes a difference in the actual process of multiplication itself. The authors are proposing the high speed and low combinational delay multiplier i.e. the fundamental block of MAC based on ancient Vedic mathematics. It enables parallel generation of partial products and eliminates unwanted multiplication steps. Multiplier architecture is based on generating all partial products and their sums in one step.

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