Area Efficient 3.3GHz Phase Locked Loop with Four Multiple Output Using 45nm VLSI Technology

Provided by: Academy & Industry Research Collaboration Center
Topic: Hardware
Format: PDF
In this paper, the author's present area efficient layout designs for 3.3GigaHertz (GHz) Phase Locked Loop (PLL) with four multiple outputs. Effort has been taken to design low power phase locked loop with multiple output, using VLSI technology. VLSI (Very-Large-Scale Integration) technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD (Computer-Aided Design) and practical experience in layout design. The proposed PLL is designed using 45 nm CMOS/VLSI technology with microwind 3.1.

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