Area Efficient 5-Input Decimal Adder

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Provided by: International Journal of Scientific Research Engineering &Technology (IJSRET)
Topic: Hardware
Format: PDF
With the increasing complexity in computation application the authors need better decimal adder which takes lesser time and less power consumption. So in this paper, they have proposed an area efficient 5-input decimal adder using sum vectors and correction bits. With the help of carry look ahead adder, generator circuit their designed decimal adders could perform efficient addition with five input operands. In their implementation after synthesize through Xilinx verilog module they get delay of 12.352 ns which is less with increased number of inputs.
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