Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
Asynchronous on-chip networks are good candidates for multi-core applications requiring low-power consumption. Asynchronous Spatial Division Multiplexing (SDM) routers provide better throughput with lower area overhead than asynchronous virtual channel routers; however, the area overhead of SDM routers is still significant due to their high-radix central switches. A new 2-stage Clos switch is proposed to reduce the area overhead of asynchronous SDM routers. It is shown that replacing the crossbars with the 2-stage Clos switches can significantly reduce the area overhead of SDM routers when more than two virtual circuits are used.
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