Area Efficient Full Subtractor Design Using CMOS Technology

Provided by: IT Society of India (ITSI)
Topic: Hardware
Format: PDF
Full subtractor is a combinational digital circuit that performs 1-bit subtraction with borrow-in. This paper is to design a 1-bit full subtractor by using CMOS 180nm technology with reduced number of transistors, and hence it efficiency in area, speed and power consumption. Two types of simulation or test bench will be performed in order to ensure that the implementation is fully functional. First, a schematic simulation will be performed by means of the "Cadence schematic editor and analog environment" software. Second, the 1-bit subtractor layout model will be emulated by the "Cadence virtuoso editor".

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