Area Efficient Higher Order FIR Filter Design Using Improved Distributed Arithmetic with Look Up Tables
In this paper, the authors describe the design and implementation of highly efficient LUT based circuit for the implementation of FIR filter using distributed arithmetic algorithm. It is a multiplier less FIR filter designed and designed based on distributed arithmetic algorithm. The DA-based technique consists of Look-Up Table (LUT), shift registers and scaling accumulator. Analysis on the performance of filter order with partition on different address length of partial tables are done using Xilinx 12.1 synthesis tool.