Area-Efficient Pipelining for FPGA-Targeted High-Level Synthesis
Traditional techniques for pipeline scheduling in high-level synthesis for FPGAs assume an additive delay model where each operation incurs a pre-characterized delay. While a good approximation for some operation types, this fails to consider technology mapping, where a group of logic operations can be mapped to a single Look-Up Table (LUT) and together incur one LUT worth of delay. The authors propose an exact formulation of the throughput-constrained and mapping aware pipeline scheduling problem for FPGA-targeted high-level synthesis with area minimization being a primary objective.
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