Area Estimation and Optimisation of FPGA Routing Fabrics

Provided by: Imperial College London
Topic: Hardware
Format: PDF
In this paper the authors present a methodology for estimating and optimizing FPGA routing fabrics using high-level modeling and convex optimization techniques. Experimental methods for exploring design spaces suffer from expensive computation time, which is exacerbated by increased dimensionality due to the larger number of architectural parameters. In this paper the authors build on previously published paper to describe a model of FPGA routing area. This model is used in conjunction with a form of optimization known as geometric programming, in order to analytically derive optimized FPGA architectural parameters, demonstrating the power and accuracy of model-based approaches in configurable architecture design.

Find By Topic