Area Overhead and Delay Analysis for Built-In-Self-Test (BIST) Technique

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Provided by: SEARCH Digital Library
Topic: Hardware
Format: PDF
As the device size is shrinking, device density is increasing. This increases the functional complexity on the chip and also accessing of internal sub-circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip is also becoming very time consuming and costly process with increasing cost. To reduce the cost of testing of chips by costly Automatic Test Equipment (ATE), Built-In-Self-Test (BIST) technique has emerged as a cheap alternative.
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